The layout design of circuits which involve the interconnection of power semiconductor die, such as synchronous buck converters for example, involves consideration of the voltage and current losses associated interconnecting the power semiconductor die. Multiple power semiconductor packages offer the benefit of short interconnects between the power devices. However, placing the multiple devices into a form factor that is easily attached to a printed circuit (PC) board together with minimizing the length of the interconnections and maximizing the cross sectional area of the interconnections to reduce the resistance and inductance of the interconnections in a package that can be economically produced is a goal of the design of multiple power semiconductor chips.